Evaluación de la fiabilidad de microprocesadores COTS mediante las infraestructuras de depuración On-Chip
##plugins.themes.bootstrap3.article.sidebar##
ISSN: 1680-8894
E-ISSN: 2219-6714
Sección
Artículos
Artículos
Esta obra está bajo licencia internacional Creative Commons Reconocimiento-NoComercial-SinObrasDerivadas 4.0.
##plugins.themes.bootstrap3.article.main##
Enviado:
Jun 6, 2017
Publicado: Jun 6, 2017
Publicado: Jun 6, 2017
Resumen
Este artículo presenta una herramienta de inyección de fallos y la metodología para la realización de campañas de inyección de Single-Event-Upsets (SEUs) en microprocesadores Commercial-off-the-shelf (COTS). Este método utiliza las ventajas que ofrecen las infraestructuras de depuración de los microprocesadores actuales, además del depurador estándar de GNU (GDB) para la ejecución y depuración de los programas de pruebas. Los experimentos desarrollados sobre microprocesadores reales, así como en las máquinas virtuales, demuestran la viabilidad y la flexibilidad de la propuesta como una solución de bajo costo para evaluar la fiabilidad de los microprocesadores COTS
Palabras clave
Commercial-off-the-shelf (COTS), depuración integrada en el chip, efectos de la radiación, fiabilidad de microprocesadores, inyección de fallos, errores lógicosDescargas
La descarga de datos todavía no está disponible.
##plugins.themes.bootstrap3.article.details##
Cómo citar
Isaza-González, J., Serrano-Cases, A., Restrepo-Calle, F., Cuenca-Asensi, S., & Martínez-Álvarez, A. (2017). Evaluación de la fiabilidad de microprocesadores COTS mediante las infraestructuras de depuración On-Chip. I+D Tecnológico, 13(1), 5-14. Recuperado a partir de https://revistas.utp.ac.pa/index.php/id-tecnologico/article/view/1432
Citas
(1) M. Nicolaidis, Ed., Soft Errors in Modern Electronic Systems, vol. 41. Boston, MA: Springer US, 2011.
(2) R. C. Baumann, “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 305–315, Sep. 2005.
(3) P. Shivakumar, M. D. Kistler, S. W. Keckler, D. C. Burger, and L. Alvisi, “Modeling the effect of technology trends on the soft error rate of combinational logic,” Dependable Syst. Networks, 2002. DSN 2002. Proceedings. Int. Conf., pp. 389– 398, 2002.
(4) T. Karnik, P. Hazucha, and J. Patel, “Characterization of soft errors caused by single event upsets in CMOS processes,” IEEE Trans. Dependable Secur. Comput., vol. 1, no. 2, pp. 128–143, 2004.
(5) F. Wang and V. D. Agrawal, “Single Event Upset: An Embedded Tutorial,” in 21st International Conference on VLSI Design (VLSID 2008), 2008, pp. 429–434.
(6) H. Quinn, P. Graham, J. Krone, M. Caffrey, and S. Rezgui, “Radiation-induced multi-bit upsets in SRAM-based FPGAs,” Nucl. Sci. IEEE Trans., vol. 52, no. 6, pp. 2455–2461, 2005.
(7) H. M. Quinn, D. a. Black, W. H. Robinson, and S. P. Buchner, “Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing,” IEEE Trans. Nucl. Sci., vol. 60, no. 3, pp. 2119–2142, 2013.
(8) P. Folkesson, S. Svensson, and J. Karlsson, “A comparison of simulation based and scan chain implemented fault injection,” in Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224), 1998, pp. 284–293.
(9) D. Alexandrescu, L. Sterpone, and C. López-Ongil, “Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation,” 19th IEEE Eur. Test Symp., 2014.
(10) R. V. T. Calin, M. Nicolaidis, “Upset hardened memory design for submicron CMOS technology,” . IEEE- Transactions-on-Nuclear-Science, vol. 43, no. 6, pp. 2874– 2878, 1996.
(11) L. Antoni, R. Leveugle, and M. Feher, “Using run-time reconfiguration for fault injection in hardware prototypes,” in 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings., 2002, pp. 245–253.
(12) M. Portela-Garcia, C. Lopez-Ongil, M. Garcia Valderas, and L. Entrena, “Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures,” IEEE Trans. Dependable Secur. Comput., vol. 8, no. 2, pp. 308–314, Mar. 2011.
(13) L. Parra et al., “Efficient Mitigation of Data and Control Flow Errors in Microprocessors,” IEEE Trans. Nucl. Sci., vol. 61, no. 4, pp. 1590–1596, 2014.
(14) J. Isaza-Gonzalez, A. Serrano-Cases, F. Restrepo-Calle, S. Cuenca-Asensi, and A. Martinez-Alvarez, “Dependability evaluation of COTS microprocessors via on-chip debugging facilities,” in 2016 17th Latin-American Test Symposium (LATS), 2016, pp. 27–32.
(15) R. Velazco, S. Rezgui, and R. Ecoffet, “Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection,” IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2405–2411, 2000.
(16) A. V. Fidalgo, M. G. Gericota, G. R. Alves, and J. M. Ferreira, “Real-time fault injection using enhanced on-chip debug infrastructures,” Microprocess. Microsyst., vol. 35, no. 4, pp. 441–452, 2011.
(17) S. A. Chekmarev and A. M. F. Reshetnev, “Modification of Fault Injection Method via On-Chip Debugging for Processor Cores of Systems-On-Chip,” pp. 1–4, 2015.
(18) Junjie Peng, Jun Ma, Bingrong Hong, and Chengjun Yuan, “Validation of Fault Tolerance Mechanisms of an Onboard System,” in 2006 1st International Symposium on Systems and Control in Aerospace and Astronautics, pp. 1230–1234.
(19) M. Portela-Garcia, C. Lopez-Ongil, M. Garcia-Valderas, and L. Entrena, “A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors,” in 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007, pp. 101–106.
(20) Rajesh Venkatasubramanian, J. P. Hayes, and B. T. Murray, “Low-cost on-line fault detection using control flow assertions,” in 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., pp. 137–143.
(21) A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, I. Solcia, and L. Tagliaferri, “FAUST: fault-injection script-based tool,” in 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., p. 160.
(22) A. Martínez-Álvarez, F. Restrepo-Calle, L. A. Vivas Tejuelo, and S. Cuenca-Asensi, “Fault tolerant embedded systems design by multi-objective optimization,” Expert Syst. Appl., vol. 40, no. 17, pp. 6813–6822, 2013.
(2) R. C. Baumann, “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 305–315, Sep. 2005.
(3) P. Shivakumar, M. D. Kistler, S. W. Keckler, D. C. Burger, and L. Alvisi, “Modeling the effect of technology trends on the soft error rate of combinational logic,” Dependable Syst. Networks, 2002. DSN 2002. Proceedings. Int. Conf., pp. 389– 398, 2002.
(4) T. Karnik, P. Hazucha, and J. Patel, “Characterization of soft errors caused by single event upsets in CMOS processes,” IEEE Trans. Dependable Secur. Comput., vol. 1, no. 2, pp. 128–143, 2004.
(5) F. Wang and V. D. Agrawal, “Single Event Upset: An Embedded Tutorial,” in 21st International Conference on VLSI Design (VLSID 2008), 2008, pp. 429–434.
(6) H. Quinn, P. Graham, J. Krone, M. Caffrey, and S. Rezgui, “Radiation-induced multi-bit upsets in SRAM-based FPGAs,” Nucl. Sci. IEEE Trans., vol. 52, no. 6, pp. 2455–2461, 2005.
(7) H. M. Quinn, D. a. Black, W. H. Robinson, and S. P. Buchner, “Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing,” IEEE Trans. Nucl. Sci., vol. 60, no. 3, pp. 2119–2142, 2013.
(8) P. Folkesson, S. Svensson, and J. Karlsson, “A comparison of simulation based and scan chain implemented fault injection,” in Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224), 1998, pp. 284–293.
(9) D. Alexandrescu, L. Sterpone, and C. López-Ongil, “Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation,” 19th IEEE Eur. Test Symp., 2014.
(10) R. V. T. Calin, M. Nicolaidis, “Upset hardened memory design for submicron CMOS technology,” . IEEE- Transactions-on-Nuclear-Science, vol. 43, no. 6, pp. 2874– 2878, 1996.
(11) L. Antoni, R. Leveugle, and M. Feher, “Using run-time reconfiguration for fault injection in hardware prototypes,” in 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings., 2002, pp. 245–253.
(12) M. Portela-Garcia, C. Lopez-Ongil, M. Garcia Valderas, and L. Entrena, “Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures,” IEEE Trans. Dependable Secur. Comput., vol. 8, no. 2, pp. 308–314, Mar. 2011.
(13) L. Parra et al., “Efficient Mitigation of Data and Control Flow Errors in Microprocessors,” IEEE Trans. Nucl. Sci., vol. 61, no. 4, pp. 1590–1596, 2014.
(14) J. Isaza-Gonzalez, A. Serrano-Cases, F. Restrepo-Calle, S. Cuenca-Asensi, and A. Martinez-Alvarez, “Dependability evaluation of COTS microprocessors via on-chip debugging facilities,” in 2016 17th Latin-American Test Symposium (LATS), 2016, pp. 27–32.
(15) R. Velazco, S. Rezgui, and R. Ecoffet, “Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection,” IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2405–2411, 2000.
(16) A. V. Fidalgo, M. G. Gericota, G. R. Alves, and J. M. Ferreira, “Real-time fault injection using enhanced on-chip debug infrastructures,” Microprocess. Microsyst., vol. 35, no. 4, pp. 441–452, 2011.
(17) S. A. Chekmarev and A. M. F. Reshetnev, “Modification of Fault Injection Method via On-Chip Debugging for Processor Cores of Systems-On-Chip,” pp. 1–4, 2015.
(18) Junjie Peng, Jun Ma, Bingrong Hong, and Chengjun Yuan, “Validation of Fault Tolerance Mechanisms of an Onboard System,” in 2006 1st International Symposium on Systems and Control in Aerospace and Astronautics, pp. 1230–1234.
(19) M. Portela-Garcia, C. Lopez-Ongil, M. Garcia-Valderas, and L. Entrena, “A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors,” in 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007, pp. 101–106.
(20) Rajesh Venkatasubramanian, J. P. Hayes, and B. T. Murray, “Low-cost on-line fault detection using control flow assertions,” in 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., pp. 137–143.
(21) A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, I. Solcia, and L. Tagliaferri, “FAUST: fault-injection script-based tool,” in 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., p. 160.
(22) A. Martínez-Álvarez, F. Restrepo-Calle, L. A. Vivas Tejuelo, and S. Cuenca-Asensi, “Fault tolerant embedded systems design by multi-objective optimization,” Expert Syst. Appl., vol. 40, no. 17, pp. 6813–6822, 2013.